Publications

Journal Papers

2022
J15 - [O-JSSC’21]. A 3.7 mW 12.5 MHz 81dB-SNDR 4th-Order Continuous-time DSM with Single-OTA and 2nd-Order Noise-shaping SAR
- Lu Jie, Xiyuan Tang, Jiaxin Liu, Linxiao Shen, Shaolan Li, Nan Sun, and Michael P Flynn
- IEEE Open Journal of the Solid-State Circuits Society (O-JSSC), 2022
2021
J14 - [JSSC’20]. A software-defined always-on system with 57–75-nW wake-up function using asynchronous clock-free pipelined event-driven architecture and time-shielding level-crossing ADC
- Zhixuan Wang, Hao Zhang, Yihan Zhang, Linxiao Shen, Jiayoon Ru, Haitao Fan, Zhichao Tan, Yangyuan Wang, Le Ye, and Ru Huang
- IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 9, pp. 2804-2816, Sept. 2021
J13 - [TCAS-I’21]. The challenges and emerging technologies for low-power artificial intelligence IoT systems
- Le Ye, Zhixuan Wang, Ying Liu, Peiyu Chen, Heyi Li, Hao Zhang, Meng Wu, Wei He, Linxiao Shen, Yihan Zhang, Zhichao Tan, Yangyuan Wang, and Ru Huang
- IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 4821-4834, Dec. 2021
J12 - [JSSC’21]. A 148-nW reconfigurable event-driven intelligent wake-up system for AIoT nodes using an asynchronous pulse-based feature extractor and a convolutional neural network
- Zhixuan Wang, Ying Liu, Peng Zhou, Zhichao Tan, Haitao Fan, Yihan Zhang, Linxiao Shen, Jiayoon Ru, Yangyuan Wang, Le Ye, and Ru Huang
- IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 11, pp. 3274-3288, Nov. 2021.
J11 - [O-JSSC’21]. An overview of noise-shaping SAR ADC: From fundamentals to the frontier
- Lu Jie, Xiyuan Tang, Jiaxin Liu, Linxiao Shen, Shaolan Li, Nan Sun, and Michael P Flynn
- IEEE Open Journal of the Solid-State Circuits Society (O-JSSC), vol. 1, pp. 149-161, 2021.
J10 - [JSSC’21]. Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array
- Heyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Linxiao Shen, Jiayoon Ru, Yihan Zhang, Le Ye, and Ru Huang
- IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 12, pp. 3560-3572, Dec. 2021.
2020
J9 - [JSSC’20]. A Two-Step ADC with a Continuous-Time SAR Based First Stage
- Linxiao Shen, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu, and Nan Sun
- Accepted to IEEE Journal of Solid-State Circuits (JSSC), (ISSCC invited).
J8 - [JSSC’20]. An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier
- Xiyuan Tang, Linxiao Shen* (Corresponding), Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Pan, and Nan Sun
- Accepted to IEEE Journal of Solid-State Circuits (JSSC), (VLSI symposium invited).
J7 - [JSSC’20]. A 10b 120MS/s SAR ADC with Reference Ripple Cancellation
- Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, and Nan Sun
- Accepted to IEEE Journal of Solid-State Circuits (JSSC), (CICC invited).
J6 - [JSSC’20]. A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-based Sensor Readout Circuit in a Hybrid PLL- ΔΣM Structure
- Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, and Nan Sun
- Accepted to IEEE Journal of Solid-State Circuits (JSSC), (CICC invited).
2019
J5 - [JSSC’19]. A Second-Order Purely VCO-Based CT ΔΣ ADC using a Modified DPLL in 40nm CMOS
- Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu and Nan Sun
- Accepted to IEEE Journal of Solid-State Circuits (JSSC).
J4 - [AMT’19]. Modular and Reconfigurable Wireless E-Tatoos for Personalized Sensing
- Hyoyoung Jeong, Liu Wang, Taewoo Ha, Ruchika Mitbander, Xiangxing Yang, Zhaohe Dai, Shutao Qiao, Linxiao Shen, Nan Sun, Nanshu Lu
- Adv. Mater. Technol. 2019, 1900117.
J2 - [SSCL’19]. A 1 GS/s 20 MHz-BW Capacitive-Input Continuous-Time ∆Σ ADC Using a Novel Parasitic Pole-Free Fully Differential VCO
- Abhishek Mukherjee, Miguel Gandara, Biying Xu, Shaolan Li, Linxiao Shen, and Nan Sun
- IEEE Solid-State Circuit Letter (SSC-L), 2019
2018
J1 - [JSSC’18]. A 1-V 0.25-uW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor
- Linxiao Shen, Nanshu Lu, and Nan Sun
- IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 3, pp. 896-905, March 2018.

Patents

Till 2022
P1. Inverter stacking amplifier
- Linxiao Shen, Nan Sun
- US patent number 11223335
P2. Continuous-time SAR ADC
- Linxiao Shen, Nan Sun
- US application pending.

Conference Papers

2022
C19 - [CICC’22]. A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme
- Hao Zhang, Linxiao Shen, Shichuang Zhang, Heyi Li, Yihan Zhang, Zhichao Tan, Ru Huang, Le Ye
- 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022
C18 - [ISCAS’22]. A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
- Xinhang Xu, Siyuan Ye, Jihang Gao, Linxiao Shen, Le Ye
- IEEE international symposium on Circuits and Systems (ISCAS), 2022.
C17 - [ISSCC’22]. An 82nW 0.53 pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique
- Ying Liu, Zhixuan Wang, Wei He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang
- 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022
C16 - [ISSCC’22]. Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53 fW/bit Leakage for AIoT Sensing Platforms
- Yihan Zhang, Chang Xue, Xiao Wang, Tianyi Liu, Jihang Gao, Peiyu Chen, Jinguang Liu, Linan Sun, Linxiao Shen, Jiayoon Ru, Le Ye, Ru Huang
- 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022
2021
C15 - [ISSCC’21]. 10.4 A 3.7 mW 12.5 MHz 81dB-SNDR 4th-order CTDSM with single-OTA and 2nd-order NS-SAR
- Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun
- 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021
C14 - [ISSCC’21]. 27.7 A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR
- Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun
- 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021
2020
C13 - [ISSCC’20]. A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
- Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun
- IEEE international Solid-State Circuits Conference (ISSCC), 2020, to appear (accepted)
C12 - [ISSCC’20]. A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
- Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Pan, and Nan Sun
- IEEE international Solid-State Circuits Conference (ISSCC), 2020, to appear (accepted)
2019
C11 - [ISSCC’19]. A 0.01mm2 25uW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
- Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, and Nan Sun
- IEEE international Solid-State Circuits Conference (ISSCC), 2019
C10 - [VLSI sym.’19]. A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF and Chopping
- Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, and Nan Sun
- 2019 IEEE Symposium on VLSI Circuits, Kyoto, 2019, to appear (accepted)
C9 - [ISSCC’19]. A 16fJ/conversion-step Time-Domain Incremental Zoom Capacitance-to-Digital Converter
- Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal Hall, and Nan Sun
- IEEE international Solid-State Circuits Conference (ISSCC), 2019
C8 - [VLSI sym.’19]. An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier
- Xiyuan Tang, Begum Kasap, Linxiao Shen (Corresponding), Xiangxing Yang, Wei Shi, and Nan Sun
- 2019 IEEE Symposium on VLSI Circuits, Kyoto, 2019
C7 - [DAC’19]. WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout
- Biying Xu, Yibo Lin, Shaolan Li, Linxiao Shen, Nan Sun, and David Pan
- Design Automation Conference (DAC), 2019.
C6 - [CICC’19]. A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-based Sensor Readout Circuit in a Hybrid PLL- ΔΣM Structure
- Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, and Nan Sun
- Custom integrated circuits conference (CICC), 2019.
C5 - [CICC’19]. A 10b 100MS/s SAR ADC with Reference Ripple Cancellation
- Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, and Nan Sun
- Custom integrated circuits conference (CICC), 2019.
C4 - [ISPD’19]. Device Layer-Aware Analytical Placement for Analog Circuits
- Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yobo Lin, Nan Sun, and David Z. Pan
- IEEE International symposium of physical design (ISPD), 2019.
2018
C3 - [ASSCC’18]. A Second-Order Purely VCO-Based CT ΔΣ ADC using a Modified DPLL in 40nm CMOS
- Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, and Nan Sun
- IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, 2018
2017
C2 - [EMBC’17]. NFC-Enabled, Tattoo-Like Stretchable Biosensor Manufactured by ‘Cut-and-Paste’ Method
- Hyoyoung Jeong, Taewoo Ha, Irene Kuang, Linxiao Shen, Zhaohe Dai, Nan Sun, and Nanshu Lu
- 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Seogwipo, 2017
C1 - [VLSI sym.’17]. A 1V 0.25uW Inverter-Stacking Amplifier With 1.07 Noise Efficiency Factor
- Linxiao Shen, Nanshu Lu, and Nan Sun
- 2017 Symposium on VLSI Circuits, Kyoto, 2017

Linxiao Shen

Publications

Journal Papers

J15 - [O-JSSC’21]. A 3.7 mW 12.5 MHz 81dB-SNDR 4th-Order Continuous-time DSM with Single-OTA and 2nd-Order Noise-shaping SAR

J14 - [JSSC’20]. A software-defined always-on system with 57–75-nW wake-up function using asynchronous clock-free pipelined event-driven architecture and time-shielding level-crossing ADC

J13 - [TCAS-I’21]. The challenges and emerging technologies for low-power artificial intelligence IoT systems

J12 - [JSSC’21]. A 148-nW reconfigurable event-driven intelligent wake-up system for AIoT nodes using an asynchronous pulse-based feature extractor and a convolutional neural network

J11 - [O-JSSC’21]. An overview of noise-shaping SAR ADC: From fundamentals to the frontier

J10 - [JSSC’21]. Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array

J9 - [JSSC’20]. A Two-Step ADC with a Continuous-Time SAR Based First Stage

J8 - [JSSC’20]. An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier

J7 - [JSSC’20]. A 10b 120MS/s SAR ADC with Reference Ripple Cancellation

J6 - [JSSC’20]. A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-based Sensor Readout Circuit in a Hybrid PLL- ΔΣM Structure

J5 - [JSSC’19]. A Second-Order Purely VCO-Based CT ΔΣ ADC using a Modified DPLL in 40nm CMOS

J4 - [AMT’19]. Modular and Reconfigurable Wireless E-Tatoos for Personalized Sensing

J2 - [SSCL’19]. A 1 GS/s 20 MHz-BW Capacitive-Input Continuous-Time ∆Σ ADC Using a Novel Parasitic Pole-Free Fully Differential VCO

J1 - [JSSC’18]. A 1-V 0.25-uW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor

Patents

P1. Inverter stacking amplifier

P2. Continuous-time SAR ADC

Conference Papers

C19 - [CICC’22]. A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme

C18 - [ISCAS’22]. A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

C17 - [ISSCC’22]. An 82nW 0.53 pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique

C16 - [ISSCC’22]. Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53 fW/bit Leakage for AIoT Sensing Platforms

C15 - [ISSCC’21]. 10.4 A 3.7 mW 12.5 MHz 81dB-SNDR 4th-order CTDSM with single-OTA and 2nd-order NS-SAR

C14 - [ISSCC’21]. 27.7 A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR

C13 - [ISSCC’20]. A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation

C12 - [ISSCC’20]. A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

C11 - [ISSCC’19]. A 0.01mm2 25uW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor

C10 - [VLSI sym.’19]. A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF and Chopping

C9 - [ISSCC’19]. A 16fJ/conversion-step Time-Domain Incremental Zoom Capacitance-to-Digital Converter

C8 - [VLSI sym.’19]. An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier

C7 - [DAC’19]. WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout

C6 - [CICC’19]. A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-based Sensor Readout Circuit in a Hybrid PLL- ΔΣM Structure

C5 - [CICC’19]. A 10b 100MS/s SAR ADC with Reference Ripple Cancellation

C4 - [ISPD’19]. Device Layer-Aware Analytical Placement for Analog Circuits

C3 - [ASSCC’18]. A Second-Order Purely VCO-Based CT ΔΣ ADC using a Modified DPLL in 40nm CMOS

C2 - [EMBC’17]. NFC-Enabled, Tattoo-Like Stretchable Biosensor Manufactured by ‘Cut-and-Paste’ Method

C1 - [VLSI sym.’17]. A 1V 0.25uW Inverter-Stacking Amplifier With 1.07 Noise Efficiency Factor